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Data Sheet
SERIAL PRESENCE-DETECT MATRIX
Rev.1.1
09.06.2010
BYTE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DESCRIPTION
NUMBER OF SPD BYTES USED
TOTAL NUMBER OF BYTES IN SPD DEVICE
FUNDAMENTAL MEMORY TYPE
NUMBER OF ROW ADDRESSES ON ASSEMBLY
NUMBER OF COLUMN ADDRESSES ON ASSEMBLY
NUMBER OF PHYSICAL BANKS ON DIMM
MODULE DATA WIDTH
MODULE DATA WIDTH (continued)
MODULE VOLTAGE INTERFACE LEVELS (V DDQ )
SDRAM CYCLE TIME, (t CK )
(CAS LATENCY =2.5 (2700, 2100) ; CL=3* (3200)
SDRAM ACCESS FROM CLOCK, (t AC )
(CAS LATENCY =2.5 (2700, 2100); CL=3* (3200))
MODULE CONFIGURATION TYPE
REFRESH RATE/ TYPE
SDRAM DEVICE WIDTH (PRIMARY SDRAM)
ERROR- CHECKING SDRAM DATA WIDTH
MINIMUM CLOCK DELAY, BACK- TO- BACK
RANDOM COLUMN ACCESS
BURST LENGTHS SUPPORTED
NUMBER OF BANKS ON SDRAM DEVICE
CAS LATENCIES SUPPORTED
CS LATENCY
WE LATENCY
SDRAM MODULE ATTRIBUTES
SDRAM DEVICE ATTRIBUTES: GENERAL
SDRAM CYCLE TIME, (t CK )
(CAS LATENCY=2(2700, 2100) CL=2,5*(3200))
SDRAM ACCESS FROM CK, (t AC )
(CAS LATENCY=2(2700, 2100) CL=2.5*(3200)
SDRAM CYCLE TIME, (t CK )
(CAS LATENCY=1.5(2700, 2100) CL=2*(3200))
SDRAM ACCESS FROM CK, (t AC )
(CAS LATENCY=1.5(2700, 2100) CL=2*(3200)
MINIMUM ROW PRECHARGE TIME, (t RP )
MINIMUM ROW ACTIVE TO ROW ACTIVE, (t RRD )
MINIMUM RAS# TO CAS# DELAY, (t RCD )
MINIMUM RAS# PULSE WIDTH, (t RAS )
MODULE BANK DENSITY
3200-3033
0x50
0x70
0x1C
0x60
0x70
0x75
0x75
0x3C
0x28
0x3C
0x28
0x80
0x08
0x07
0x0D
0x0A
0x01
0x40
0x00
0x04
0x00
0x82
0x10
0x00
0x01
0x0E
0x04
0x01
0x02
0x20
0xC0
0x40
2700-2533
0x60
0x70
0x0C
0x75
0x70
0x00
0x00
0x48
0x30
0x48
0x2A
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